1. Field of the Invention
The present invention relates to a gate electrode structure of a memory cell of a nonvolatile semiconductor memory.
2. Description of the Related Art
A memory cell of a nonvolatile semiconductor memory such as a NAND-type flash memory has a stack gate structure comprised a floating gate and a control gate electrode. Data-program/erase is performed in such a manner that a threshold of the memory cell is caused to change by moving electric charges between a silicon substrate and the floating gate while utilizing Fowler-Nordheim (FN) tunneling.
Here, in order to cause the nonvolatile semiconductor memory to function as a nonvolatile semiconductor memory, a high threshold and a low threshold should be distinguished accurately while making variation width (margin) of the threshold of the memory cell larger than a fixed width.
However, in recent years, in order to lower price per bit, miniaturization of the memory cell has been promoted noticeably. When the memory cell is miniaturized, variation width of the threshold becomes small because of interference between adjacent memory cells. In order to solve this problem, a technique for accurately controlling the variation width of the threshold becomes necessary.
However, control of the variation width of the threshold becomes difficult by a leak produced at an insulating layer between a floating gate and a control gate electrode. This leak is generally called an inter-polysilicon dielectric (IPD) leak because its insulating layer is called the inter-polysilicon dielectric.
The IPD leak becomes particularly noticeable at the time of programming, that is, when electrons are injected into the floating gate from the silicon substrate. Specifically, the threshold of the memory cell is hard to be controlled because, even though electrons are injected into the floating gate from the silicon substrate, at the same time, electrons are emitted from the floating gate to the control gate electrode by the IPD leak.